U.S. Pat. No. 4,460,982 (hereinafter, Gee et al) discloses an intelligent EEPROM. During both programming and erasing, the device disclosed by Gee et al iteratively applies pulses of programming voltage to the memory cell or cells being accessed and, between pulses, compares the state of the cells to the desired end state.
The advantages of an intelligent EEPROM over a "dumb" device are well known. Among these are the relative ease with which such a device may be integrated with a microprocessor-controlled system. Prior to the Gee et al invention, a microprocessor writing to an EEPROM was required to control the application and timing of the programming voltage to the EEPROM, thus precluding the execution of other tasks during the relatively long program/erase cycles.
In a microprocessor-controlled system using EEPROMs according to Gee et al, and as further described hereinbelow, the microprocessor is free to continue the execution of other tasks after having instructed the intelligent EEPROM to write a data value to a particular location. However, if the microprocessor issues a read instruction to the EEPROM while the write cycle is being executed, the memory is unavailable. In other words, the read request must be held pending until the previously issued write request is completed. Since the time required to program an EEPROM cell is very long compared to the speed at which a typical microprocessor operates, such a system may have an unacceptably long worst case read latency; that is, the time required to complete a read operation after the request is first issued.